Seeed Studio XIAO RP2040
Compact RP2040-based microcontroller with USB-C and WS2812 RGB LED
The Seeed Studio XIAO RP2040 is a compact microcontroller board built around the Raspberry Pi RP2040 dual-core ARM Cortex-M0+ chip. It features a USB-C connector, an onboard NeoPixel RGB LED, and 14 I/O pins in a stamp-form-factor footprint.
Datasheet
Section titled “Datasheet”The full RP2040 datasheet is available here. It covers the complete GPIO function table, memory map, peripheral register descriptions, and clock tree.
Peripherals
Section titled “Peripherals”| Peripheral | Support | Notes |
|---|---|---|
| GPIO | ✅ | |
| I2C | ✅ | |
| SPI | ✅ | |
| UART | ✅ | |
| PWM | ✅ | |
| USB CDC | ✅ | TX only. Output sent before DTR assertion is lost. |
| Timer | ✅ | |
| Watchdog | ✅ | |
| Flash / XIP | ✅ | |
| ADC | ⚠️ | Reads return fixed stub values; no analogue conversion is performed. Includes channel 4 (internal temperature sensor), also not simulated. |
| PIO | ✅ | |
| DMA | ✅ | |
| Clocks / PLL | ✅ | |
| Pads | ✅ | Drive strength, slew rate, schmitt trigger, pull configuration. |
| Resets | ✅ | Per-subsystem reset control. |
| RTC | ❌ |
- ✅ Fully supported
- ⚠️ Partial / stub
- ❌ Not supported
Dual-Core
Section titled “Dual-Core”The RP2040 has two Cortex-M0+ cores. CPU1 is halted by default. Firmware that launches it via the SIO FIFO bootrom entry sequence will start it and both cores run concurrently.
Debug Output
Section titled “Debug Output”| Channel | Description |
|---|---|
| RTT | SEGGER Real-Time Transfer log output. Requires the _SEGGER_RTT control block symbol to be present in the ELF. |
| USB CDC | Lines written to the virtual USB serial port. Firmware must wait for DTR assertion before sending or output during early boot will be lost. |
Both channels feed the terminal panel in real time.
Limitations
Section titled “Limitations”-
Boot button has no effect — DFU and bootloader mode are not simulated
-
USB CDC output is TX only — host-to-device writes are not forwarded to firmware
-
ADC returns stub values — no analogue conversion is performed
-
The processor is designed to be throughput limited at 1 MIPS. Timing behavior (intervals) remains unaffected; only instruction execution speed is reduced.