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Raspberry Pi Pico 2

RP2350 board with dual Cortex-M33 cores, the full 40-pin header, and a genuine bootrom boot path

Raspberry Pi Pico 2 board

The Raspberry Pi Pico 2 carries the RP2350 — dual Cortex-M33 cores with TrustZone, 520 KB of SRAM, and 4 MB of external QSPI flash. Firmware boots through the real bootrom path, the same sequence silicon runs, rather than being dropped straight at main().

It takes an ELF or a raw .bin.

The RP2350 datasheet and Pico 2 datasheet cover the register map, bootrom, and board pinout.

All 40 header positions are wirable.

GroupPins
GPIOGP0GP22, GP26GP28 (26 total)
GroundGND, GND2GND8 — eight physically distinct pads
PowerVBUS, VSYS, 3V3 (out)
Control3V3_EN, RUN, ADC_VREF

GP23, GP24, GP25 and GP29 are not on the header — on a real Pico 2 they are wired internally (SMPS mode select, VBUS sense, onboard LED, VSYS sense), so they are deliberately absent rather than silently doing nothing.

BusDefault pins
I2C0GP4 (SDA) / GP5 (SCL) — the pico-sdk default
PeripheralSupportNotes
SIO / IO_BANK0 / PADSHardware-validated against a real Pico 2
UARTuart0, uart1
I2CIncluding slave mode
SPI
PWM
Timers / tickstimer0, timer1
Bootrom / XIP flashReal boot path, including XIP aliases
XOSC / PLL / clocks
DMA
PIOpio0pio2
Watchdog, POWMAN
TRNG, SHA-256, DCP
TrustZone / access controlHardware-validated
ADC⚠️Present; conversions are not modelled
USB⚠️Present; enumeration is not modelled
HSTX⚠️Present; no output modelled
  • ✅ Fully supported ⚠️ Partial / stub ❌ Not supported

GP25 drives the onboard LED. It isn’t a header pin, so it can’t be wired — it lights in the editor, and every transition is recorded as a state change you can read back with run.logs({ from: "pico2:onboard_led" }).

UART output is captured per tap: a uart0 channel appears when firmware prints, and uart1 alongside it as soon as it’s used.

  • ADC returns stub values — no analogue conversion is performed
  • USB does not enumerate; BOOTSEL / DFU mode is not modelled
  • The second core starts only when firmware launches it through the normal SIO FIFO sequence